Method and apparatus for producing bonded dielectric separation wafer

ABSTRACT

The present invention provides a method for producing a bonded dielectric separation wafer in which an auto-alignment can be carried out with reference to the orientation flat of a supporting substrate wafer after the wafer bonding step, and also an apparatus to be used for bonding wafers. When wafers are placed one upon another, the silicon wafers  10, 20  are irradiated with transmission light in order to capture the transmission images thereof. The positions of the pattern of dielectric isolation grooves  13  in the silicon wafer  10  and the orientation flat  20   a  of the silicon wafer  20  are determined from the images and the bonding position of the wafers  10, 20  is determined based on the determined positions. Auto-alignment of the bonded dielectric separation wafer can thereby be carried out with reference to the orientation flat  20   a  of the silicon wafer  20  after the wafer bonding step.

FIELD OF THE INVENTION

[0001] The present invention relates to a method and an apparatus forproducing a bonded dielectric separation wafer, and in more specific, toa method for producing such a bonded dielectric separation wafer havinga certain physical relationship established between a position of anorientation flat, “OF”, of a supporting substrate wafer and a positionof a pattern of dielectric isolation grooves of an active layer waferand also to an apparatus used for bonding those wafers.

DESCRIPTION OF THE PRIOR ART

[0002] In the prior art, a bonded dielectric separation wafer has beenproduced through respective steps shown in FIGS. 5 and 6.

[0003] In one prior art method, at first, a silicon wafer 10 having amirror-polished surface is fabricated and prepared in accordance with awell-known method, which will be formed into an active layer wafer (seeFIG. 5(a)). This silicon wafer 10 has an orientation flat “OF” formedtherein. Secondary, a mask oxide film 11 is formed on a surface of thissilicon wafer 10 (FIG. 5(b)). Further, after a photo resist 12 isdeposited over the mask oxide film 11, the photo lithography method isapplied to form openings in predetermined locations (in a predeterminedpattern) thereof. Then, the mask oxide film 11 exposed through theseopenings is removed so as to form windows of predetermined pattern inthe mask oxide film 11. Consequently, the top surface of the siliconwafer 10 can be partially exposed through these windows. Then, after thephoto resist 12 is removed, this silicon wafer 10 is dipped in analkaline etchant (IPA/KOH/H₂O) to anisotropically etch the inside of thewindow defined on the top surface of the wafer (FIG. 5(c)). Throughthese steps, V-shaped dielectric isolation grooves 13 are formed in thesurface of the wafer.

[0004] In a subsequent step, this mask oxide film 11 is cleaned andremoved using a dilute hydrofluoric acid solution or a bufferhydrofluoric acid solution (FIG. 5(d)). Then, a dielectric separationoxide film 14 is formed on the surface of the silicon wafer 10 through athermal oxidation processing (FIG. 5(e)). As a result, the dielectricseparation oxide film 14 having a predetermined thickness is formed overthe surface of the silicon wafer 10 including the surfaces of thedielectric isolation grooves 13.

[0005] Subsequently, this silicon wafer 10 is coated with a seedpolysilicon layer 15 over the surface thereof, i.e., over the dielectricseparation oxide film 14, up to a predetermined thickness. After that, ahigh temperature CVD method is applied at the temperature of about 1200to 1300° C. so as for a high temperature polysilicon layer 16 to growover the dielectric separation oxide film 14 until it reaches thethickness of about 150 μm (FIG. 5(f)). After that, a peripheral portionof this silicon wafer 10 is beveled. In a subsequent step, polishing isapplied to a back surface of this silicon wafer 10 so as to removeundesired portion of high temperature polysilicon, which has expanded tocover partially the back surface, thus to obtain a flat surface. Then,grinding and polishing are carried out until the high temperaturepolysilicon layer 16 on the top surface of the silicon wafer 10 becomesabout 10 to 80 μm thick (FIG. 6(g)).

[0006] After that, a low-temperature CVD method is applied at atemperature in the range of 550 to 700° C. so as for a low-temperaturepolysilicon layer 17 to grow over the surface of the silicon wafer 10 upto 1 to 5 μm thick. In order to flatten a bonding surface, the topsurface of this low-temperature polysilicon layer 17 is mirror-polished(FIG. 6(g)).

[0007] On the other hand, a silicon wafer 20 covered with a siliconoxide film 21 is prepared separately from said silicon wafer 10, whichwill function as a supporting substrate wafer (FIG. 6(h)). A surface ofthis silicon wafer 20 has also been mirror-polished. In addition, thissilicon wafer 20 has been processed to have the orientation flat.

[0008] Then, this silicon wafer 20 is bonded with the other siliconwafer 10 prepared for the active layer wafer as described above, withthe mirror-polished surfaces thereof contacting to each other (FIG.6(i)). Thus, a base material of the bonded wafer has been fabricated.

[0009] After that, a thermal processing is applied to thus bonded waferto enhance its bonding strength.

[0010] Then, as shown in FIG. 6(j), the peripheral region of this bondedwafer in the active layer wafer side is beveled. Specifically, thegrinding is applied to the bonded wafer from the top surface of thesilicon wafer 10 at an oblique angle such that a portion as defined topass through the bonding interface and to reach the surface layer of thesilicon wafer 20 may be cut off.

[0011] Then, the top surface of the bonded wafer in the active layerwafer side is ground and further polished (FIG. 6 (k)). The volume to beground and polished off from the active layer wafer should be determinedsuch that the dielectric separation oxide film 14 may be partiallyexposed to the outside and thus dielectric separation silicon islands10A separated from each other by the dielectric separation oxide film 14may appear on top of the high temperature polysilicon layer 16. It is tobe noted that the silicon oxide film 21 will be removed by the HFcleaning after the above step.

[0012] In this method according to the prior art as discussed above,after the high temperature polysilicon layer 16 having grown on thesilicon wafer 10, the beveling process is applied thereto to remove thepolysilicon deposited on the peripheral region of the wafer. However, inpractice, it is impossible to carry out this removing processcompletely, and typically, a part of the polysilicon should be left inthe peripheral region of the wafer in order to avoid the reduceddiameter of the silicon wafer 10 owing to an excessive grinding.

[0013] This means that the polysilicon layers may also be left in theorientation flat (OF) portion of the silicon wafer 10.

[0014] This has often led to such a situation in which after thebeveling, the “OF” formed by the residual high temperature polysiliconlayer 16 is not in the parallel relationship with the “OF” of thesilicon wafer 10.

[0015] Generally, the bonding of the wafers is carried out in such amanner that the “OF” of the active layer wafer and the “OF” of thesupporting substrate wafer should be matched and then, in one example,the both wafers are bonded to each other from the central portionstoward the peripheral portions thereof so as to increase the bondedarea. In this manner, the two wafers can be bonded to each other, whilekeeping a certain physical relationship between the “OF” of thesupporting substrate wafer and the grid pattern of the dielectricisolation grooves formed on the active layer wafer. In specific, thehorizontal dielectric isolation grooves or structural elements of thegrid pattern in parallel with Y-direction in FIG. 4 are set to be inparallel with the “OF” of the wafer for the supporting substrate. As aresult from this setting, auto-alignment with reference to the “OF” ofthe supporting substrate wafer will be effective in each consecutiveprocessing step following this bonding step.

[0016] However, whether or not this auto-alignment will effectively workdepends on the condition of the “OF” portion of the active layer wafer,that the “OF” of the high temperature polysilicon layer should be inparallel with the original “OF” inherent to the active layer wafer. Thisis because the pattern of the dielectric isolation grooves is externallyshielded with the high temperature polysilicon layer and accordingly itwould not be possible to bond the supporting substrate wafer to theactive layer wafer while visually observing the “OF” of the supportingsubstrate wafer and the horizontal grooves of said pattern on the activelayer wafer and keeping the parallel relationship therebetween on thescreen of a monitor, for example. That is, if the “OF” of the hightemperature polysilicon layer is not parallel with the “OF” of theactive layer wafer, the auto-alignment could not be carried out in anyconsecutive steps, such as an exposing process, for example.

SUMMARY OF THE INVENTION

[0017] The present invention has been made in the light of the problemsdescribed above, and an object thereof is to provide a method forproducing a bonded dielectric separation wafer which allows anauto-alignment to be carried out with reference to an orientation flat“OF” of a supporting substrate wafer after a wafer bonding step, and anapparatus used for bonding those wafers.

[0018] The invention as defined in claim 1 provides a method forproducing a bonded dielectric separation wafer comprising the steps of:growing a polysilicon layer on a top surface of an active layer waferwhich has dielectric isolation grooves in a predetermined pattern havingformed therein with reference to an orientation flat thereof and hasbeen covered with a dielectric separation oxide film; polishing a topsurface of the polysilicon layer; fabricating a bonded wafer by bondingthe polished surface of the active layer wafer to a surface of asupporting substrate wafer having an orientation flat; beveling aperipheral portion of the bonded wafer; and after the beveling step,applying grinding and polishing to a back surface of the active layerwafer thereby making appear in the polished surface a plurality ofdielectric separation silicon islands isolated by the dielectricseparation oxide film; wherein in said bonding step, a transmissionlight, which may pass through the wafers, is used to detect a positionof the pattern of the dielectric isolation grooves in the active layerwafer and a position of the orientation flat of the supporting substratewafer, and based on the detected positions, the pattern of thedielectric isolation grooves of the active layer wafer and theorientation flat of the supporting substrate wafer are adjusted to fallin a certain physical relationship, and thereafter the bonding of thetwo wafers is carried out with the physical relationship held asadjusted.

[0019] A high temperature CVD method represents such a method in which asource gas containing silicon is introduced into a reactor together witha carrier gas (such as a H₂ gas) to cause silicon, which has beengenerated by heat decomposition or reduction of the source gas, to bedeposited on a heated silicon wafer. Typically a chemical compoundcontaining silicon, such as SiCl₂H₂, SiHCl₃ and SiCl₄, is used therefor.

[0020] As for the reactor, for example, a pancake reactor or a cylinderreactor may also be employed.

[0021] The temperature used in growing of the high temperaturepolysilicon may be varied depending on the heating system employed inthe reactor. In a vertical reactor, for example, which is most typicallyused in this application, preferably the temperature is within a rangeof 1200 to 1290° C., more preferably within a range of 1230 to 1280° C.At the temperature below 1200° C., disadvantageously the silicon waferis apt to be broken. On the other hand, the temperature higher than1290° C. disadvantageously may cause a slip, leading an irregular bowingor a breaking of the silicon wafer.

[0022] The polysilicon layer may be grown to be such thick that will beequal to a thickness defined by multiplying the depth of anisotropicetching required for forming the dielectric isolation grooves by 2 to 3and further adding a thickness of the polysilicon layer desired to beleft. The polysilicon layer not as 2 times thick as the depth of theapplied anisotropic etching sometimes could not be sufficient to fill upthe etching grooves. On the other hand, the polysilicon layer more than3 times thicker leads to undesired growth, meaning it to beuneconomical.

[0023] The etchant to be used in this anisotropic etching may includeKOH(IPA/KOH/H₂O), KOH(KOH/H₂O), and KOH(hydrazine/KOH/H₂O). As for theanisotropic etching condition, a conventional condition may be appliedthereto.

[0024] Generally applicable conditions may be employed in each processrequired for forming a window portion in a resist film lying on the topsurface of the wafer for the anisotropic etching.

[0025] The transmission light as discussed above is not limited to butmay be any light that can pass through respective wafers. For example,an infrared ray or an X-ray may be used. In the case where the siliconwafer is used, the infrared ray having a wave length of 1.1 microns (μm)or longer may be used. For the wafer of GaAs, the infrared ray havingthe wave length of 0.9 μm or longer may be used.

[0026] A transmission image of the active layer wafer and a transmissionimage of the supporting substrate wafer captured by the transmissionlight may be visually observed, for example, on a monitor screen.Consequently, an operation of placing those transmission images with oneon the other can be executed on that monitor screen.

[0027] In the present invention as defined in claim 1, based on thosetransmission images, the pattern in the active layer wafer and theorientation flat of the supporting substrate wafer may be adjusted tofall in a certain physical relationship.

[0028] In this context, adjusting the pattern in the active layer waferand the orientation flat of the supporting substrate wafer into acertain physical relationship means that, for example, an extendingdirection of the lateral grooves which are structural elements of thegrid pattern is set to be parallel with the orientation flat of thesupporting substrate wafer. Alternately, the grooves in the otherdirection (the longitudinal grooves) may be positioned to be orthogonalto the “OF” of the supporting substrate wafer.

[0029] The present invention as defined in claim 2 provides a method forproducing a bonded dielectric separation wafer in accordance with claim1, in which an extending direction of the dielectric isolation grooveson said active layer wafer is set to be parallel with the orientationflat of the supporting substrate wafer.

[0030] The present invention as defined in claim 3 provides a method forproducing a bonded dielectric separation wafer in accordance with claim1 or 2, in which the active layer wafer and the supporting substratewafer are both silicon wafers and further an infrared ray is used as thetransmission light.

[0031] The present invention as defined in claim 4 provides a method forproducing a bonded dielectric separation wafer comprising the steps of:growing a polysilicon layer on a top surface of an active layer waferwhich has dielectric isolation grooves in a predetermined pattern havingformed therein with reference to an orientation flat thereof and hasbeen covered with a dielectric separation oxide film; polishing a topsurface of the polysilicon layer; fabricating a bonded wafer by bondingthe polished surface of the active layer wafer to a surface of asupporting substrate wafer having an orientation flat; beveling aperipheral portion of the bonded wafer; and after the beveling step,applying grinding and polishing to a back surface of the active layerwafer thereby making appear in the polished surface a plurality ofdielectric separation silicon islands isolated by the dielectricseparation oxide film; wherein in said bonding step, a transmissionlight, which may pass through the wafers, is used to detect a positionof the orientation flat of the active layer wafer and a position of theorientation flat of the supporting substrate wafer, and based on thedetected positions, the two orientation flats are matched with eachother, and thereafter the bonding of the active layer wafer and thesupporting substrate wafer is carried out with the physical relationshiptherebetween held as matched.

[0032] The present invention as defined in claim 5 provides a method forproducing a bonded dielectric separation wafer in accordance with claim4, in which the active layer wafer and the supporting substrate waferare both silicon wafers and further an infrared ray is used as thetransmission light.

[0033] The present invention as defined in claim 6 provides an apparatusfor bonding wafers, comprising: a first holding means for holding anactive layer wafer; a second holding means for holding a supportingsubstrate wafer; a positioning means for determining proper positionsfor placing one upon another of the active layer wafer and thesupporting substrate wafer held by the first and the second holdingmeans, respectively; and a bonding means for bonding the active layerwafer to the supporting substrate wafer, after the positions for placingthe wafers one upon another having been determined, wherein saidpositioning means has a transmission detecting section for detectingrespective portions in respective wafers working as markers in placingthe wafers one upon another based on a transmission image of thesupporting substrate wafer and another transmission image of the activelayer wafer, each image captured as a result of irradiation of atransmission light capable of passing through those wafers, and executesthe positioning of the active layer wafer and the supporting substratewafer for placing one upon another based on the detected result from thetransmission detecting section.

[0034] As for the first and the second holding means, for example, awafer retainer plate utilizing a vacuum chuck may be employed.

[0035] As for the bonding means, for example, such an apparatus that canmove the active layer wafer and the supporting substrate wafer indirections so as for the bonding surfaces thereof to come closer to eachother may be employed. At that time, only the active layer wafer may bemoved. Or otherwise, only the supporting substrate wafer may be moved.Alternatively, both of the wafers may be moved.

[0036] The marker for the supporting substrate wafer and the marker forthe active layer wafer, which are used for placing one wafer on theother wafer is not limited. For example, the maker for the former may bethe pattern of the dielectric isolation grooves in the active layerwafer or the orientation flat of the active layer wafer. Further, themarker for the latter may be the orientation flat of the supportingsubstrate wafer.

[0037] If the transmission light is the infrared ray, the infrared rayirradiated from an infrared illumination source (the transmission lightcapable of passing through the wafer) can be observed by an infrared TVcamera. As the infrared TV camera may be used an infrared ray vidiconcamera tube sensitive to the wave length in a range up to 1.9 μm. It isa matter of course that an image formed on the infrared TV camera may bemade clearer to see with the aid of a contrast enhancing function, forexample.

[0038] According to the present invention, after the polysilicon havinggrown, the peripheral region of the active layer wafer is beveled andthen the bonding position of the active layer wafer with the supportingsubstrate wafer should be determined.

[0039] At that time, the transmission light is used to capture thetransmission images of the active layer wafer and the supportingsubstrate wafer. From those two transmission images, the position of themarker (the pattern or the orientation flat) in the active layer waferand the position of the marker (the orientation flat) in the supportingsubstrate wafer for placing wafers one upon another are detected,respectively, and then based on the respective detection results, thepositions of the active layer wafer and the supporting substrate waferare determined for placing one upon another. After the positioninghaving been determined, the both wafers are bonded to each other thus tofabricate the bonded wafer.

[0040] With this positioning completed, the auto-alignment of the bondeddielectric separation wafer with reference to the orientation flat ofthe supporting substrate wafer could be carried out in the processingsteps (e.g., the exposing process) subsequent to the wafer bonding step.

[0041] The orientation flat for those wafers may be a main “OF” or a sub“OF”. The sub “flat” may be formed in a location at an angle of 90 or 45degrees with respect to the main “flat” along the circumferentialdirection.

[0042] According to the present invention, since the positions of theactive layer wafer and the supporting substrate wafer for placing oneupon another are determined from the positions of the markers in theboth wafers for placing one on another captured by irradiating thetransmission light against them, therefore the auto-alignment of thebonded dielectric separation wafer can be carried out with reference tothe orientation flat of the supporting substrate wafer in the stepssubsequent to the wafer bonding step.

BRIEF DESCRIPTION OF THE DRAWINGS

[0043]FIG. 1 is a schematic diagram for illustrating a wafer bondingapparatus used in a method for producing a bonded dielectric separationwafer according to one embodiment of the present invention;

[0044]FIG. 2 is a sectional view for illustrating respective stepsincluded in the method for producing the bonded dielectric separationwafer according to the embodiment of the present invention;

[0045]FIG. 3 is also a sectional view for illustrating respective stepsincluded in the method for producing the bonded dielectric separationwafer according to the embodiment of the present invention;

[0046]FIG. 4 is a plan view for illustrating a step for placing wafersone upon another in the method for producing the bonded dielectricseparation wafer according to the embodiment of the present invention;

[0047]FIG. 5 is a sectional view for illustrating steps for producing abonded dielectric separation wafer according to the prior art; and

[0048]FIG. 6 is a sectional view for illustrating steps for producingthe bonded dielectric separation wafer according to the prior art.

PREFERRED EMBODIMENTS FOR IMPLEMANTING THE PRESENT INVENTION

[0049] A method for producing a bonded dielectric separation waferaccording to a preferred embodiment of the present invention will now bedescribed. It is to be noted that the explanation in this specificationis directed to the method, as an example, for producing a bondeddielectric separation wafer which has been described in connection withthe prior art. Accordingly, the same reference numerals are used todesignate the same components. For the convenience of the explanation,one direction within a horizontal plane is designated as an X-direction,another direction orthogonal to the X-direction within the horizontalplane as a Y-direction and another direction along a vertical plane as aZ-direction.

[0050] At first, a silicon wafer 10 with a diameter in a range of 4 to 6inches having a mirror polished surface is fabricated and prepared,which will be formed into an active layer wafer (FIG. 2(a)). A surfaceorientation should be (100). An orientation flat “OF” (a main flat) hasbeen formed in a peripheral region thereof.

[0051] In next step, this silicon wafer 10 is cleaned.

[0052] After that, a mask oxide film (a SiO₂ film) 11 having a thicknessof, for example, 1 μm is formed on a top surface of this silicon wafer(FIG. 2(b)). It may be formed, foe example, by thermal oxidation.Alternatively, a nitride film (SiN_(X)), instead of the mask oxide film11, may be grown by the CVD method.

[0053] Then, a known photolithography method is used to form a photoresist film 12 on this mask oxide film 11. After that, in accordancewith a well-known method, windows in a predetermined pattern (e.g., agrid pattern) are formed in this photo resist film 12 (FIG. 2(c)).

[0054] Subsequently, the mask oxide film 11 is etched through thosewindows thus to form the same pattern of windows, thereby partiallyexposing the top surface of the silicon wafer 10. After that, the photoresist film 12 is removed (again FIG. 2 (c)). Then, the surface of thewafer is cleaned.

[0055] Subsequently, the silicon wafer 10 is dipped in an anisotropicetchant (IPA/KOH/H₂O) for a predetermined period so as to etch thesurface of the wafer with this mask oxide film 11 used as a masking.This etching forms concavities (recesses) in a predetermined pattern onthe top surface of the silicon wafer.

[0056] In specific, the anisotropic etching is applied to the topsurface of the silicon wafer 10, and as a result, dielectric isolationgrooves 13, each having a V-shaped section with a depth of 70 to 80 μmare formed thereon (again FIG. 2(c)).

[0057] In next step, this mask oxide film 11 is cleaned and removedusing, for example, a dilute HF solution (FIG. 2(d)).

[0058] After that, the silicon wafer is doped with dopant if necessary,and then a dielectric separation oxide film 14 is formed over the topsurface (also over the back surface) of the wafer up to a predeterminedthickness by way of the thermal oxidation processing (FIG. 2(e)). Atthat time, the dielectric separation oxide film 14 is also formed overan inner wall surface of the dielectric isolation grooves 13.

[0059] In the next step, the surface of the silicon wafer 10 is cleaned.

[0060] Subsequently, the silicon wafer 10 is coated with a seedpolysilicon layer 15 over the top surface thereof, i.e., over thedielectric separation oxide film 14 in the top surface side, up to apredetermined thickness (FIG. 2(f)). After the coating, the surfacethereof is cleaned.

[0061] In the next step, a high temperature CVD method is applied at thetemperature of about 1200 to 1300° C. so as for a high temperaturepolysilicon layer 16 to grow over the seed polysilicon layer 15 up toabout 150 μm thick (again FIG. 2(f)). A vertical reactor and a knownmethod may be used.

[0062] In further step, the polysilicon deposited on the peripheralregion of the silicon wafer 10 is beveled within a range not to touchthe inner silicon wafer. For beveling, a known beveling wheel may beused.

[0063] Subsequently, the back surface of the silicon wafer 10 ispolished so as to remove an undesired portion of the high temperaturepolysilicon which has extended excessively to cover a part of the waferback surface, thereby flattening the back surface (FIG. 3(g)). Thepolishing may be carried out using a known polishing material andpolishing cloth.

[0064] Then, the high temperature polysilicon layer 16 on the topsurface of the wafer is ground and polished until it reaches thethickness in a range of 10 to 80 μm (FIG. 3(g)). After the grinding witha grinding wheel having been applied, the ground surface is polished inthe known manner.

[0065] After that, a low-temperature CVD method is applied at atemperature in the range of 550 to 700° C. so as for a low-temperaturepolysilicon layer 17 to grow over the top surface of the silicon waferup to 1 to 5 μm thick. This may be carried out under the knownconditions and in the known equipment.

[0066] Then, in order to flatten the bonding surface, the top surface ofthis low temperature polysilicon layer 17 is mirror polished (again FIG.3(g)). This may be carried out by using a known polishing agent and aknown polishing cloth.

[0067] On the other hand, another silicon wafer 20 in the same size asthe silicon wafer 10, covered with a silicon oxide film 21 and having amirror-polished surface is prepared, which will work as a supportingsubstrate wafer (FIG. 3(h)). The orientation flat “OF” has been alsoformed therein similarly to the silicon wafer 10.

[0068] Subsequently, a relational positioning is carried out between thesilicon wafer 20 and the silicon wafer 10 for the active layer wafer inorder to place them one upon another with their mirror polished surfacesfacing to each other.

[0069] Then, the two wafers 10 and 20 are brought into contact with eachother thus to be bonded (FIG. 3(i)). For example, this may be carriedout in such a manner that the bonding area may be increased from thecentral portion toward the peripheral region.

[0070] Herein, the positioning step for placing the silicon wafer 10 andthe silicon wafer 20 one upon another and the bonding step by the use ofwafer bonding apparatus 30 will be described in more detail withreference to FIG. 1.

[0071] As shown in FIG. 1, the wafer bonding apparatus 30 comprises awafer retainer plate (a first holding means) 31 for holding the siliconwafer 10 and another wafer retainer plate (a second holding means) 32for holding the silicon wafer 20. The wafer bonding apparatus 30 furthercomprises a pair of XY-tables (a positioning means) 33 and 34 which movethe respective wafers 10 and 20 along the orthogonal directions(X-direction and Y-direction) within a horizontal plane, respectivelyand determine the positions of the wafers 10, 20 for placing one uponanother, and a pair of elevation cylinders (a bonding means) 35 and 36which are mounted on the corresponding XY-tables 33 and 34 respectivelyand move the wafers 10 and 20 to come closer to each other fordetermining the positions for placing them one upon another or otherwiseto press and thus bond the wafers 10 and 20 to each other in the bondingstep. Also, this wafer bonding apparatus 30 further comprises atransmission detecting section 37 for irradiating an infrared ray(transmission light) which passes through both wafers 10 and 20, anddetecting from the captured transmission images the positions of thepattern of the dielectric isolation grooves on the silicon wafer 10 andthe “OF” 20 a of the silicon wafer 20, which are functioning as markersfor placing the wafers one upon another, and a control section 38 forcontrolling respective components of the apparatus.

[0072] Both of the wafer retainer plates 31, 32 are of the vacuum chucktype. In one exemplary configuration, a plurality of suction ports incommunication with a negative pressure source are opened inpredetermined locations on the wafer retainer plates 31 and 32.

[0073] The XY-tables 33 and 34 are operatively disposed in opposite toeach other as spaced by a predetermined distance along the Z-directionyet maintaining the parallel relationship therebetween so as to becapable of moving within the horizontal plane. Specifically, in thisconfiguration, each of the XY-tables 33 and 34 may be driven by adriving motor in the X-direction and by another driving motor in theY-direction so as to move in the specified directions. It is to be notedthat those XY-tables 33 and 34 may be configured to be free to rotaterespectively, within the horizontal planes. In this case, the XY-table,together with the driving motor, may be fixedly installed on a machinebase which in turn, is rotated by an actuator.

[0074] An elevation cylinder 35 and another elevation cylinder 36 arevertically installed on an upper surface of the lower XY-table 33 and onan under surface of the upper XY-table 34, respectively.

[0075] The elevation cylinder 35 disposed in the lower side has itspiston rod protruding upward and holds said wafer retainer plate 31fixedly attached to a top end of the piston rod in the horizontaldirection.

[0076] The elevation cylinder 36 disposed in the upper side has itspiston rod protruding downward and holds said wafer retainer plate 32fixedly attached to the top end of the piston rod in the horizontaldirection.

[0077] As a result of the configuration described above, the waferretainer plate 31 and the wafer retainer plate 32 are disposed inopposite to each other with a predetermined interval therebetween.Further, those wafer retainer plates 31 and 32 are adapted to comecloser to and to move away from each other.

[0078] The siliconwafers 10 and 20 are respectively sucked onto thewafer retainer plates 31 and 32, with their mirror polished surfacesfacing to each other.

[0079] The transmission detecting section 37 comprises an emissionsection 39 disposed above the peripheral edges of those silicon wafers10, 20 and a light acceptance section 40 disposed below the peripheraledges of those silicon wafers 10, 20, wherein the infrared rayirradiated from the emission section 39 is received by the lightacceptance section 40. The emission section 39 comprises an infraredillumination source for irradiating the infrared ray at a predeterminedwave length. The acceptance section 40 comprises an infrared ray TV(television) camera having an infrared ray vidicon camera tube, and animage created by the received light can be displayed on a TV monitor.

[0080] A control section 38 controls the infrared ray to be output fromthe emission section 39 and the incoming light input from the acceptancesection 40, respectively. For example, the control section 38 controlsthe infrared ray of specified waver length to be output for a specifiedtime period and at the same time controls the contrast in an incominglight signal to be enhanced so as to output it to the monitor as atransmission image. Further, the control section 38 controls therespective outputs of the XY-tables 33, 34 and the elevation cylinders35, 36. The control section 38 may be composed of a computer systemcomprising, for example, a CPU, a ROM, a RAM, an I/O and so on.

[0081] An operation of this wafer bonding apparatus 30 will now beexplained.

[0082] At first, the apparatus handles the silicon wafers 10 and 20transferred by robot hands or the like in such a manner that the siliconwafer 10 may be sucked by the wafer retainer plate 31 having its suctionface directed upward and the silicon wafer 20 may be sucked by the waferretainer plate 32 having its suction face directed downward.

[0083] After that, the silicon wafers 10 and 20 are moved by theXY-tables 33 and 34 in the X- and Y-directions respectively, within thehorizontal planes to approximate locations for placing them one uponanother. In this step, the “OF” 10 a of the silicon wafer 10 isapproximately matched to the “OF” 20 a of the silicon wafer 20 in planview. At that time, the emission section 39 and the light acceptancesection 40 are disposed above and below both “OFs” 10 a, 20 a.

[0084] Then, the piston rods of the elevation cylinders 35 and 36 arerespectively protruded in the Z-direction to cause the silicon wafers 10and 20 to come closer to each other until the gap between them reducesdown to about 1 mm. At that time, a few pieces of wedges may be insertedinto a space between the peripheral regions of the two silicon wafers10, 20 so that a certain distance may be always kept between the twosilicon wafers 10 and 20.

[0085] Subsequently, the infrared ray is irradiated from the emissionsection 39 toward the “OFs” 10 a, 20 a, which have been set in thepositions for placing the wafers one upon another. The irradiatedinfrared ray passes through the silicon wafers 10, 20 in theirperipheral edge portions and a set of detection data for them is sent tothe control section 38, which is in turn displayed as the transmissionimages representative of the silicon wafers 10, 20 on the monitorscreen. After that, based on these transmission images, the controlsection 38 instructs the XY-table 33 to move in the XY-direction so thatthe pattern of the dielectric isolation grooves 13 may be fall in aspecific physical relationship with respect to the “OF” 20 a (i.e., sothat the parallel relationship between the lateral grooves and the “OF”may be established). This may allow the “OF” 20 a to be positioned inparallel with the respective dielectric isolation grooves (lateralgrooves) 13 in the Y-direction even if the polysilicon layer 16 inhibitsthe dielectric isolation grooves 13 from being visually observed.

[0086] It is to be noted that during anisotropic etching of thedielectric isolation grooves 13, each of the dielectric isolationgrooves 13 in the Y direction has been anisotropically etched so as tobe in parallel with the “OF” 10 a with reference to the “OF” 10 a of thesilicon wafer 10. This means the “OF” 10 a and the “OF” 20 a, after thetwo wafers having been bonded to each other, should be in the parallelrelationship (see FIG. 4). In this regard, in this drawing, the “OF” 16a of the high temperature polysilicon layer 16 (an apparent “OF” of thesilicon wafer 10) is not in the parallel relationship with respect tothe either “OF” 10 a or 20 a.

[0087] Since the present invention has employed such a manner fordetermining the position for placing the wafers one upon another byusing the infrared ray, therefore in each consecutive step after thewafer bonding step, the auto-alignment of the bonded dielectricseparation wafer with reference to the “OF” 20 a can be carried out.

[0088] After that, in order to enhance the bonding strength of the thusobtained bonded wafer, thermal processing is applied to the wafer (againFIG. 3(i)). For example, a know thermal processing at a temperature of1100° C. for the bonding may be carried out.

[0089] In the next step, the beveling is applied to the peripheralregion of the active layer wafer portion of the bonded wafer topartially cut it off as shown in FIG. 3(j). A known beveling wheel maybe used.

[0090] Then, the top surface on the side of the active layer wafer ofthis bonded wafer is ground and the ground surface is further polished(FIG. 3(k)). The volume to be ground off from the active layer wafershould be determined such that the dielectric separation oxide film 14may be partially exposed to the outside and thus the dielectricseparation silicon islands 10A separated from each other by thedielectric separation oxide film 14 may appear on top of the hightemperature polysilicon layer 16. After that, the silicon oxide film 21may be removed by the HF cleaning at any adequate times. Thus, thebonded dielectric separation wafer has been fabricated.

[0091] Further, after that, in a device manufacturing process, a desireddevice will be fabricated on the dielectric separation silicon islands10A. In this case, for example, in the exposing process, the orientationflat “OF” 20 a of the supporting substrate wafer described above mayserve as the reference for the auto-alignment.

[0092] It is to be noted that although in the above description withrespect to the transmission images, the dielectric isolation grooves inthe Y-direction are used to establish the parallel relationship with the“OF” of the supporting substrate wafer, yet alternatively, theorientation flat of the active layer wafer and the “OF” of thesupporting substrate wafer may be matched to each other.

What is claimed is:
 1. A method for producing a bonded dielectricseparation wafer comprising the steps of: growing a polysilicon layer ona top surface of an active layer wafer which has dielectric isolationgrooves in a predetermined pattern having formed therein with referenceto an orientation flat thereof and has been covered with a dielectricseparation oxide film; polishing a top surface of the polysilicon layer;fabricating a bonded wafer by bonding the polished surface of saidactive layer wafer to a surface of a supporting substrate wafer havingan orientation flat; beveling a peripheral portion of said bonded wafer;and after the beveling step, applying grinding and polishing to a backsurface of said active layer wafer thereby making appear in the polishedsurface a plurality of dielectric separation silicon islands isolated bythe dielectric separation oxide film, wherein in said bonding step, atransmission light, which may pass through the wafers, is used to detecta position of said pattern of the dielectric isolation grooves in saidactive layer wafer and a position of said orientation flat of saidsupporting substrate wafer, and based on the detected positions, saidpattern of the dielectric isolation grooves of said active layer waferand said orientation flat of said supporting substrate wafer areadjusted to fall in a certain physical relationship, and thereafter thebonding of the two wafers is carried out with said physical relationshipheld as adjusted.
 2. A method for producing a bonded dielectricseparation wafer in accordance with claim 1, in which an extendingdirection of said dielectric isolation grooves on said active layerwafer is set to be parallel with said orientation flat of saidsupporting substrate wafer.
 3. A method for producing a bondeddielectric separation wafer in accordance with claim 1 or 2, in whichsaid active layer wafer and said supporting substrate wafer are bothsilicon wafers and further an infrared ray is used as said transmissionlight.
 4. A method for producing a bonded dielectric separation wafercomprising the steps of: growing a polysilicon layer on a top surface ofan active layer wafer which has dielectric isolation grooves in apredetermined pattern having formed therein with reference to anorientation flat thereof and has been covered with a dielectricseparation oxide film; polishing a top surface of said polysiliconlayer; fabricating a bonded wafer by bonding the polished surface ofsaid active layer wafer to a surface of a supporting substrate waferhaving an orientation flat; beveling a peripheral portion of said bondedwafer; and after the beveling step, applying grinding and polishing to aback surface of said active layer wafer thereby making appear in thepolished surface a plurality of dielectric separation silicon islandsisolated by the dielectric separation oxide film, wherein in saidbonding step, a transmission light, which may pass through the wafers,is used to detect a position of said orientation flat of said activelayer wafer and a position of said orientation flat of said supportingsubstrate wafer, and based on the detected positions, said twoorientation flats are matched with each other, and thereafter thebonding of said active layer wafer and said supporting substrate waferis carried out with the physical relationship therebetween held asmatched.
 5. A method for producing a bonded dielectric separation waferin accordance with claim 4, in which said active layer wafer and saidsupporting substrate wafer are both silicon wafers and further aninfrared ray is used as said transmission light.
 6. An apparatus forbonding wafers, comprising: a first holding means for holding an activelayer wafer; a second holding means for holding a supporting substratewafer; a positioning means for determining proper positions for placingone upon another of said active layer wafer and said supportingsubstrate wafer held by said first and said second holding means,respectively; and a bonding means for bonding said active layer wafer tosaid supporting substrate wafer after said positions for placing thewafers one upon another having been determined, wherein said positioningmeans has a transmission detecting section for detecting respectiveportions in respective wafers working as markers in placing the wafersone upon another based on a transmission image of said supportingsubstrate wafer and another transmission image of said active layerwafer, each image captured as a result of irradiation of a transmissionlight capable of passing through those wafers, and executes thepositioning of said active layer wafer and said supporting substratewafer for placing one upon another based on the detected result fromsaid transmission detecting section.